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Name: Rajeev Narayanan
Academic Rank: Assistant Professor
Department: Elect. & Comp. Engineering

Expertise Keywords: Analog & Mixed Signal (AMS) Modeling, Embedded Systems, Hardware Security, Reliability Analysis of Complex Systems, Statistical Verification, System on Chip

Available For: interviews, essays, speaking

Currrent Research: Security Analysis of Hardware Systems.
Statistical Verification of Analog and Mixed Signal Designs.

Contact Information

Office Phone: 845-257-2606
E-mail Address: narayanr@newpaltz.edu
Personal Web Site: https://faculty.newpaltz.edu/rajeevnarayanan/

Education

Colleges/
Universities
Attended
Dates
Attended
Degree
Conferred
Year
Conferred
Major
Subject
BITS, Pilani 1997-1999 M.Eng 1999 MicroElectronics
VIT 1992-1996 B.Eng 1996 Electronics & Communication Engg
Concordia University 2006-2012 PhD 2012 Electrical & Computer Engg.

Awards/Grants/Honors

IBM BRAVO Award for my contribution and initiative in MISTRAL 2.0 Project, 2003.
IBM Certificate of Merit for developing PD methodology using third party tools, 2004.
IBM Certificate of Merit for my contribution towards On Demand Community Program, 2004.
Vellore Institute of Technology Award for first rank in 6th semester, 1994.
Regroupement Strategique en Microsystems du Quebec (RESMIQ) - Scholarship, 2009.
"Best Paper Award" in Hardware Verication Group for the year 2010.

Organizational Memberships

Reviewer for
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2012.
IEEE Saudi International Electronics, Communications and Photonics Conference, 2011.
IEEE International North East Workshop on Computer Aided System, 2009 & 2011.
IEEE Formal Methods in Computer Aided Design (FMCAD), 2010 .
IEEE International Conference on Microelectronics (ICM), 2009.

Publications

Patents and Intellectual Property
R. Narayanan and N. Alagasamy. Tier Based Bandwidth Calculation for Devices Connected either Directly or through Hubs to USB 2_0 Host Controller, USIP000021779D, 2004.
R. Narayanan and N. Alagasamy. Improving the Performance of USB 2.0 Host Controller by Effective Port Sharing Mechanism for Devices Residing on Dierent Root Hub Ports, US IP000030397D, 2004.
R. Narayanan and R. Kamdar. Reducing the Time Taken by the CPU during Signal Integrity
Analysis, US6 543 031B1, 2003.

Journal(s):
R. Narayanan, M. Zaki, and S. Tahar: Using Stochastic Differential Equation for Verification
of Noise in Analog/ RF Circuits. Journal of Electronic Testing: Theory and Applications, 26(1):
97-109, Springer, 2010.
R. Narayanan, I. Seghair, M. Zaki, and S. Tahar: Run-Time Verification of Analog Circuits in
Presence of Noise and Process Variations. IEEE Transaction of VLSI (TVLSI), Under Review.

Conference(s):
R. Narayanan, A. Daghar, M. Zaki, and S. Tahar: Verifying Jitter in an Analog & Mixed Signal
Design Using Dynamic Time Warping. Proc. IEEE/ACM Design Automation and Test in Europe
(DATE'12), Accepted.
R. Narayanan, A. Daghar, M. Zaki, and S. Tahar: Using Pattern Matching for Ensuring Cor-
rectness of Oscillator Start-Up Condition. IEEE Frontiers in Analog Circuit (FAC) Synthesis and Verification, 2011.
R. Narayanan, M. Zaki, and S. Tahar: Ensuring Correctness of Analog Circuits in the Presence of Noise and Process Variation Using Pattern Matching. Proc. IEEE/ACM Design Automation and Test in Europe (DATE'11), pp. 1188-1191, 2011.
R. Narayanan, B. Akbarpour, M. H. Zaki, S. Tahar, and L. Paulson: Formal Verification of Ana-
log/RF Circuits in the Presence of Noise and Process Variation. IEEE/ACM Design, Automation
and Test in Europe (DATE'10), pp. 1309-1312, 2010.
R. Narayanan, M. Zaki and S. Tahar: Using Stochastic Differential Equation for Assertion Based Verification of Noise in Analog/RF Circuits. IEEE Mixed-Signals, Sensors, System Test Workshop (IMS3TW'09), pp. 1-8, 2009.
Z.Wang, N. Abbasi, R. Narayanan, M. Zaki, G. Al Sammane, and S. Tahar: Verification of Analog and Mixed Signal Designs using On-line Monitoring. In Proc. IEEE International Conference on Signals, Circuits and Systems (IMS3TW'09). pp. 1-6, 2009.
R. Narayanan, N. Abbasi, M. Zaki, G. Al Sammane, and S. Tahar: On the Simulation Perfor-
mance of Contemporary AMS Hardware Description Languages. IEEE International Conference on Microelectronics (ICM'08), pp.390-293, 2008.
R. Narayanan, N. Abbasi, G. Al Sammane, M. Zaki, and S. Tahar: A Comparative Study of
AMS Circuit Simulation in VHDL-AMS and SystemC-AMS. International Conference on Embedded Systems & Critical Applications (ICESA'08), pp.23-28, 2008.

Working Paper(s):
R. Narayanan, A. Daghar, M. Zaki, and S. Tahar: Ensuring Correctness of Analog Circuits Based on Pattern Matching. IEEE Transaction of VLSI (TVLSI), (13 pages).
R. Narayanan, N. Aziz, and S. Tahar: Equivalence Checking of AMS Designs in Presence of
Process Variations. IEEE Transaction of VLSI (TVLSI), (12 pages) .
R. Narayanan, I. Seghair, A. Daghar, M. Zaki, and S. Tahar: Verifying Jitter in an Analog &
Mixed Signal Design Using Dynamic Time Warping. IEEE Transaction of VLSI (TVLSI), (13
pages).