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Division of Engineering Programs

Current Mode Clocking and Synthesis


Division of Engineering Programs
Current-Mode Clocking and Synthesis Considering
Low-Power and Skew

Riadul Islam
Computer Engineering Faculty Candidate

Thursday, March 9, 2017
4 - 5 p.m.
Coykendall Science Building (CSB) Auditorium


In this talk, I will argue how technology scaling critically affects the power and frequency of modern microprocessors. I will advocate the need for low-power design in synchronous digital systems because interconnects in scaled technologies are consuming an increasingly significant amount of power. Using existing clocking schemes (from industry and academic research), I will first describe the major consumers of this power as global buses, clock distribution networks (CDNs), and synchronous signals in general. I will then discuss how an alternative signaling scheme, namely current mode (CM) signaling can save significant power while maintaining high-frequency operation.

In particular, I will present a new paradigm for clock distribution that uses current, rather than voltage, to distribute a global clock signal with reduced power consumption. While CM signaling has been used in one-to-one signals, this is the first usage in a one-to-many CDN. Following, I will introduce CMCS, the first CM clock synthesis methodology to reduce overall clock network power with low skew. The method can integrate with traditional clock routing followed by transmitter and receiver sizing. I will conclude by outlining the contributions of my research work, and a roadmap for my future research.

Riadul Islam received his B.Sc. degree in electrical and electronic engineering from Bangladesh University of Engineering and Technology (BUET), Dhaka, Bangladesh, in 2007, and the M. A. Sc. degree in electrical and computer engineering from Concordia University, Montreal, Canada, in 2011. From 2007 to 2009, he worked as a full time faculty in the department of electrical and electronic engineering of The University of Asia Pacific, Dhaka, Bangladesh. Currently he is working towards his Ph.D at the University of California Santa Cruz (UCSC) in the Computer Engineering department. In January 2017, he joined UCSC as a Graduate Student Instructor. His research interest includes Low- power digital & mixed signal circuit, embedded system, VLSI design & automation, neuromorphic computation, asynchronous VLSI design technique. Riadul Islam is a recipient of DAC Richard Newton Young Fellow award. He is a Member of IEEE, IEEE Young Professionals, IEEE CAS Society, and IEB.

Free  & Open to the General Public